1. Field of the Invention
The present invention relates to a phase locked loop. In addition, the present invention relates to a semiconductor device including the phase locked loop. Furthermore, the present invention relates to a wireless tag including the semiconductor device and an antenna.
2. Description of the Related Art
A phase locked loop (PLL) has a function to generate a clock signal which is synchronized with an inputted clock signal or a clock signal which has N times higher frequency than that of an inputted clock signal. Alternatively, the phase locked loop has a function to generate a stable clock signal when a data signal which is similar to a clock signal is inputted.
In the following Reference 1 (Japanese Published Patent Application No. H10-065525 (FIG. 5 in Page 3)), a basic structure of a phase locked loop is described.